1. Field of the Invention
The invention relates in general to a buck converter, and more particularly to a synchronous buck converter capable of constraining a shoot-through voltage.
2. Description of the Related Art
Referring to FIG. 1, a circuit diagram of a conventional synchronous buck converter is shown. The synchronous buck converter 100 receives a first DC voltage Vin and outputs adjustable second DC voltage Vout accordingly. The synchronous buck converter 100 includes a first transistor Q1, a second transistor Q2, and a filter circuit 102. The first transistor Q1 has a drain D1 for receiving the first DC voltage Vin, a gate G1 for receiving a first control signal C1, and a source S1 coupled to a node N. The second transistor Q2 has a drain D2 coupled to the node N, a gate G2 for receiving a second control signal C2, and a source S2 coupled to a constant voltage, such as a ground voltage. The filter circuit 102 is coupled to the node N for filtering AC noise off the voltage at the node N and outputting the second DC voltage Vout accordingly.
Due to the gate-drain parasitic capacitor Cgd2 existing between the drain D2 and the gate G2, and the gate-source parasitic capacitor Cgs2 existing between the gate G2 and the source S2 of the second transistor Q2, a shoot-through voltage SV is generated at the gate G2 of the second transistor Q2 when the first transistor Q1 is turned on and the first DC voltage Vin is applied to the gate-drain parasitic capacitor Cgd2 and the gate-source parasitic capacitor Cgs2 via the first transistor Q1. Referring to FIG. 2, a wave pattern diagram of the voltage VG1 at the gate G1 and the voltage VG2 at the gate G2 in FIG. 1 is shown. It can be seen from FIG. 2 that when the first transistor Q1 is turned on, the first DC voltage Vin will generate a shoot-through voltage SV at the gate G2 of the second transistor Q2. Because channel resistance of the two transistors Q1 and Q2 is not large, they will be turned on simultaneously by the shoot-though voltage SV, larger than the threshold voltage of the second transistor Q2, and then be burned down by the first DC voltage Vin if serious.
A conventional method for solving the shoot-through voltage issue is connecting a capacitor Cadd in parallel to the gate-source parasitic capacitor Cgs2. The shoot-through voltage can be reduced as the first DC voltage Vin is divided by the capacitor Cadd, the gate-source parasitic capacitance Cgs2, and the gate-drain parasitic capacitor Cgd2. However, the extra capacitor Cadd will delay the time for turning on the second transistor Q2. Because the second control signal C2 charges the capacitor Cadd first, the switching loss of the second transistor Q2 will be increased and the efficiency of the synchronous buck converter 100 be reduced. Therefore, using an extra capacitor Cadd to solve the issue the first transistor Q1 and the second transistor Q2 are burned down by the shoot-through voltage will reduce the efficiency of the synchronous buck converter 100. For this reason, it becomes an essential subject for industrials to constrain the shoot-through voltage and increase the efficiency of the synchronous buck converter.